1. Field of the Invention
The invention relates to process for fabricating semiconductor devices, and more particularly to a self-aligned contact process for fabricating semiconductor devices.
2. Description of the Related Art
The semiconductor industry is continually striving to improve the performance of semiconductor devices, while still attempting to reduce the size thereof for faster but lower cost devices. For enhancing the integration on the semiconductor, for example, in the structure of a Dynamic Random Access Memory (DRAM), reductions are proposed in the source/drain contact areas on metal oxide semiconductor (MOS). Therefore, while the areas for source/drain are reduced, the formation of contact openings on the source/drain in MOS for filling conductive material and the alignment thereof are an important task.
A self-aligned contact process is developed for resolving the above problems, which allows smaller devices to be constructed. FIGS. 1A to 1C schematically illustrate the cross-sectional representations of a conventional self-aligned contact process.
With reference to FIG. 1A, a gate oxide 105 and gate 110 are provided on a semiconductor substrate. Gate 110 is composed of a doped polysilicon layer 120 and tungsten silicide 130. Silicon nitride 140 is used as a passivation layer for gate 110.
Turning to FIG. 1B, a conformal buffer layer 150 is formed on the gate oxide 105, gate 110 and silicon nitride 140. A spacer 160 is formed on the sidewall 155 of the buffer layer 150. The material of the buffer layer 150 is silicon oxide, while the material of the spacer is silicon nitride.
Referring to FIG. 1C, an insulating layer 170 is formed by chemical vapor deposition (CVD) and then is etched by photolithography. The material of an insulating layer 170 is silicon oxide. In this process, since the top surface and the side wall of gate 110 is protected by silicon nitride 140 and spacer 160, a selective etching of silicon oxide 170 is performed to expose the substrate between the spacers 160 as a contact opening 180. However, since both of the material of the buffer layer 150 and insulating layer 170 are silicon oxide, when selectively etching the insulating layer 170, the buffer layer 150 is etched at the same time to result in a defect 190. Furthermore, in the subsequent procedure, before the conductive material fills the contact opening 180, the semiconductor substrate is stripped with RCA solution (H.sub.2 O.sub.2 /NH.sub.4 OH/H.sub.2 O solution) which can etch away the silicon oxide. During the step of stripping the substrate with RCA solution, the defect 190 is etched more to expose the tungsten silicide 130, and even to expose the doped polysilicon layer 120. When filling the contact opening 180 with conductive material for forming conductive line, the defect 190 is filled at same time. A short occurs between gate 110 and conductive line.
One approach for resolving the above-mentioned problems is to employ a thinner buffer layer 150 to reduce the possibility of etching the buffer layer 150. Typically, the thickness of the buffer layer 150 should be at least 200.ANG.. In this approach, a thickness of 100-200.ANG. for the buffer layer 150 is suggested . However, one purpose of the buffer layer 150 is to decrease the stress of the space 160 in the thermal treatment in the following procedures. Therefore, the thinner buffer layer will result in the dislocation of the substrate.
Another approach for resolving the above-mentioned problems is the formation of a buffer layer by thermal oxidation process, rather than by chemical vapor deposition as used in the conventional process. In the thermal oxidation process, the sidewall of the doped polysilicon layer and tungsten silicide layer of gate is formed on a passivation layer, while no oxide is formed on the top surface of the gate, which is silicon nitride. In such a case, the buffer layer on the sidewall of the gate is embedded in the spacer. Therefore, no defect in the buffer layer is formed during the etching process. However, an additional oxidation process is incorporated and thermal treatment results in adversely affecting the substrate, such as causing a dislocation of the substrate.
Therefore, a need exists to avoid the occurrence of short between a conductive line and a gate in the self-aligned contact process.